(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
Increased performance in EEPROMS can be achieved by increased efficiency of the programming and erase operations. In EEPROMs where a top gate controls a floating gate, improved programming and erase efficiency can be obtained by increasing the coupling ratio of the top gate to floating gate. The coupling ratio is essentially the ratio of the top gate-floating gate capacitance to the floating gate-substrate capacitance, so decreasing the floating gate-substrate capacitance relative to the top gate-floating gate capacitance increases the coupling ratio. The greater the coupling ratio the larger is the fraction of the voltage applied to the top gate that falls across the floating gate-substrate capacitor. In traditional EEPROM flash memory cells the area of the top gate-floating gate capacitor is the same as the area of the floating gate-substrate capacitor. This is illustrated in FIG. 1, which shows a cross-section of a typical design for a traditional EEPROM flash memory cell. Here is shown a semiconductor substrate, 2, in which shallow trench isolation, 10, that extends above the substrate surface, separates active regions of memory cells. The memory cells include floating gates, 18, formed from a poly 1 layer, and which are separated from ion implanted regions, 14, of the substrate by gate dielectrics, 4, thus forming the floating gate-substrate capacitors. Top gates, 22, formed from a poly 2 layer, are utilized as control gates and are separated from the floating gates by a dielectric layer, 20, thus forming the top gate-floating gate capacitors. In a traditional design the dimension of the top gate-floating gate capacitor, 24, denoted Y in FIG. 1 and the dimension of the floating gate-substrate capacitor, 26, denoted X in FIG. 1 are usually equal, and the dimensions of these capacitors perpendicular to the plane shown are equal as well. Thus the areas of these capacitors are usually equal, which limits the coupling ratio. The coupling ratio depends on the ratio of the areas so that changing both areas by the same factor does not alter the coupling ratio.
Methods to increase the coupling ratio have been disclosed which involve increasing the area of the top gate-floating gate capacitor relative to the area of the floating gate-substrate capacitor. It is important to achieve the increased area of the top gate-floating gate capacitor without increasing the cell area, and methods exist to increase the coupling ratio in such a manner. Hsieh et al., in U.S. Pat. No. 6,153,494, disclose a method to increase the coupling ratio by lateral coupling in stacked-gate flash. Lin et al., in U.S. Pat. No. 6,225,162, show a step-shaped floating gate to improve the coupling ratio of flash memory cells. Chen, U.S. Pat. No. 6140,182, discloses a memory cell in which vertical sides are used to increase the top gate-floating gate capacitance and thus increase the coupling ratio. (Other flash processes are disclosed in Sakamoto et al., U.S. Pat. No. 6,034,393 and in U.S. Pat. No. 6,312,989 to Hsieh et al. While increasing the top gate-floating gate capacitance increases the coupling ratio, considerable processing is required if the cell size is not to increase.
It is a primary objective of the invention to provide a flash memory cell with increased coupling ratio of top gate to floating gate. It is also a primary objective of the invention to provide a method of forming a flash memory cell with increased coupling ratio of top gate to floating gate. It is further primary objectives of the invention to achieve an increased coupling ratio of top gate to floating gate without increasing the cell size and without a considerable increase in processing. These objectives are achieved by a flash memory cell structure in which the floating gate is shaped so that the area of the floating gate to substrate capacitor is less than the area of the top gate to floating gate capacitor. The method of attaining such a shape for the floating gate according to the invention utilizes insulator spacers.
A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage. Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region. Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions. Top gates, comprised of conductive stripes that are perpendicular to the active regions, are disposed over floating gates from which they are separated by a top gate insulator layer.